PCIe 3.0
PCIe 3.0 (Peripheral Component Interconnect Express 3.0) is the third generation of the PCI Express interface standard, introduced by the PCI-SIG in 2010. It brought significant improvements over its predecessor, PCIe 2.0, by doubling the data transfer rate per lane. A single lane in PCIe 3.0 supports a bandwidth of 1 GB/s in each direction, translating to 2 GB/s for a full duplex connection. With a 16-lane configuration (x16), the total bandwidth increases to 32 GB/s. This leap in performance addressed the growing needs of high-performance applications, such as GPUs, storage controllers, and network cards.
https://en.wikipedia.org/wiki/PCI_Express
One of the key advancements in PCIe 3.0 was the introduction of an optimized 128b/130b encoding scheme, which reduced overhead compared to the 8b/10b encoding used in earlier versions. This improvement allowed more efficient use of the available bandwidth without increasing the clock speed significantly, ensuring compatibility with existing hardware and reducing power consumption. This made PCIe 3.0 a highly efficient and versatile standard for consumer and enterprise-grade computing systems.
https://pcisig.com/specifications/pciexpress/base
PCIe 3.0 became the de facto standard in the industry, with widespread adoption across motherboards, GPUs, and SSDs. It served as a foundational technology for several years, providing the necessary bandwidth for applications like AI, big data, and cloud computing. Despite the arrival of newer standards like PCIe 4.0 and PCIe 5.0, PCIe 3.0 remains relevant in many systems due to its robust performance and compatibility with a wide range of devices.
https://www.tomshardware.com/news/pci-express-3-0-spec-finalized,9488.html