PCIe 6.0
PCIe 6.0 (Peripheral Component Interconnect Express 6.0) is the sixth generation of the PCI Express standard, introduced by the PCI-SIG in 2022. It doubles the data transfer rate of its predecessor, PCIe 5.0, providing 8 GB/s per lane in each direction, or 16 GB/s for a full duplex connection. In a 16-lane configuration (x16), PCIe 6.0 achieves an unprecedented bandwidth of 256 GB/s. This massive increase in throughput is designed to meet the demands of emerging technologies like artificial intelligence, high-performance computing (HPC), and 5G networking.
https://en.wikipedia.org/wiki/PCI_Express
PCIe 6.0 introduces PAM4 (Pulse Amplitude Modulation with 4 levels) signaling, which replaces the NRZ (Non-Return-to-Zero) signaling used in earlier versions. PAM4 allows each clock cycle to carry twice as much data, enabling the significant bandwidth improvement without needing to increase the clock speed. The standard also incorporates Forward Error Correction (FEC) and Cyclic Redundancy Check (CRC) mechanisms to ensure data integrity at these higher speeds, addressing the challenges of signal degradation over longer distances.
https://pcisig.com/specifications/pciexpress/base
Adoption of PCIe 6.0 is anticipated in data-intensive environments, including data centers, autonomous systems, and next-generation storage solutions. It is particularly well-suited for accelerating workloads in fields such as machine learning and real-time analytics. While still in the early stages of implementation, PCIe 6.0 sets the stage for future advancements in computing by providing the infrastructure needed to support increasingly complex and data-heavy applications.
https://www.tomshardware.com/news/pcie-6-0-specification-release